Purpose of Research
Digital data management in next generation phased array radar; serial switching links for high-speed chip-chip interconnection; signal integrity challenges with differential wires; Currently, we are working on innovative modeling of the real-time digital stream of a sensor system with thousands of nodes. Such system modeling will contain address the analog front-ends, ADC, real-time processing, massive data link performance, and their impacts on final detection and tracking performance. Eventually, such effort will lead to a practical system evaluation tool for large scale and multifunctional radar sensors.
Industrial Sponsors
Lockheed Martin Corp. Xilinx. Inc. (Donation of tools and IP cores), Trundra Semiconductor (switching modeling), and others.
Current Progress
- Presentation of using OPNET on cluster modeling in this program (2010).
- New presentation given by Mr. Hernan Suarez on Oct 30, 2008
- New presentation given by Mr. Hernan Suarez on May 9,2008
- The FY07 research briefing
- The current white paper for FY08 goals and plans
- meeting presentation, 05/15/07
- introduction to RapidIO technology, by Yu Sun for his ECE5990 presentation
Project Descriptions
- meeting presentation, 05/15/07
- introduction to RapidIO technology, by Yu Sun for his ECE5990 presentation
References
- MIT's paper about MPAR: MIT develpoed a conceptual architecture for MPAR as a top-system level reference design.
- A paper about a twisted differential pair design.
- A good paper about FPGA system on-chip, similar device and developing tools are being used in this work.
- A paper about using FPGA and RapidIO in spaceborne radar system.
- A paper about parallel RIO simulation