wni.ad9361¶

Submodules¶

wni.ad9361.ad9361¶

class wni.ad9361.ad9361.AD9361(spidev_name=None)[source]¶

Bases: object

Implements some functions from C API that can be called from Python.

BE_MOREVERBOSE = 2¶

BE_VERBOSE = 1¶

DO_IDELAY = 4¶

DO_ODELAY = 8¶

MAX_SAMPLING_FREQ = 61440000¶

MIN_ATTENUATION = 0¶

REF_CLK = 40000000¶

apply_dict_config(config)[source]¶: Apply configuration from a dict.

bbpll_freq¶: Calculated based on equations on pg 20 of the AD9361 register map manual.

bist_disable()[source]¶

bist_loopback¶

bist_prbs(mode='Rx')[source]¶

bist_tone(freq=1, dB=0, mask=0, mode='rx')[source]¶: Run the built-in self-test with some defaults.

ch1_rx_rf_gain¶: Get and set channel 1 rx rf gain

ch1_tx_attenuation¶: Get and set channel 1 tx attenuation in dBm

ch2_rx_rf_gain¶: Get and set channel 2 rx rf gain

ch2_tx_attenuation¶: Get and set channel 2 tx attenuation in dBm

dig_tune(max_freq=False, flags=3)[source]¶: Tune the AD9361 digital interface. if max_freq == False, the current tx sampling frequency is the only frequency that will be tuned. Otherwise, all frequencies will be stepped through.

digital_loopback¶

disable_rx()[source]¶: Disable rx chain by setting GPIO low.

disable_tx()[source]¶: Disable rx chain by setting GPIO low.

enable_rx()[source]¶: Disable rx chain by setting GPIO low.

enable_tx()[source]¶: Disable rx chain by setting GPIO low.

ensm_mode¶

init()[source]¶: Initializes the ad9361, configuring clocks and stuff.

mask_read(reg, mask)[source]¶

mask_write(reg, mask, value)[source]¶

recalibrate()[source]¶

reg_read(reg)[source]¶: Read the specified register.

reg_write(reg, val)[source]¶: Write val at reg address.

reset()[source]¶: Resets the ad9361 using GPIO if possible

rf_dc_calib()[source]¶

rf_loopback¶

rx_bbdc_tracking¶: Get or set tx auto cal state

rx_clk_delay¶: Get and set the rx clk delay amounts. When the sampling clock changes, these values need to change as well.

rx_data_delay¶: Get and set the rx data delay amounts. When the sampling clock changes, these values need to change as well.

rx_frequency¶: The receive center frequency of the radar, taking into account a UDC if it is present.

rx_lo_freq¶: Get or set the current receive LO frequency (Hz)

rx_quad_tracking¶: Get or set tx auto cal state

rx_rf_bandwidth¶

rx_rfdc_tracking¶: Get or set tx auto cal state

set_rx_fir_config()[source]¶

set_rx_gain_control_mode(mode)[source]¶: Sets the gain control mode for both channels.

set_rx_lo_internal_external(int_ext)[source]¶: Set whether the LO is internal or external

set_tx_fir_config()[source]¶

set_tx_lo_internal_external(int_ext)[source]¶: Set whether the LO is internal or external

settings_as_dict()[source]¶: Return current transceiver settings as a dict.

tx_auto_cal¶: Get or set tx auto cal state

tx_clk_delay¶: Get and set the tx clk delay amounts. When the sampling clock changes, these values need to change as well.

tx_data_delay¶: Get and set the tx data delay amounts. When the sampling clock changes, these values need to change as well.

tx_frequency¶: The transmit center frequency of the radar, taking into account a UDC if it is present.

tx_lo_freq¶: Get or set the current transmit LO frequency (Hz)

tx_quad_calib()[source]¶

tx_rf_bandwidth¶: Get the tx bandwidth in Hz.

tx_sampling_freq¶: Get or set the tx sampling frequency.

Warning

The sample clock from the AD9361 goes into the FPGA. Setting the sampling frequency must always be accompanied by resetting the sysfs file fir_aresetn.

class wni.ad9361.ad9361.BistMode[source]¶

Bases: enum.IntEnum

An enumeration.

DISABLE = 0¶

INJ_RX = 2¶

INJ_TX = 1¶

class wni.ad9361.ad9361.ENSMMode[source]¶

Bases: enum.IntEnum

An enumeration.

ALERT = 2¶

FDD = 3¶

PINCTRL = 6¶

PINCTRL_FDD_INDEP = 7¶

RX = 1¶

SLEEP = 5¶

TX = 0¶

WAIT = 4¶

wni.ad9361.ad9361_swig¶

class wni.ad9361.ad9361_swig.AD9361_InitParam[source]¶

Bases: object

ad9361_rfpll_ext_recalc_rate¶

ad9361_rfpll_ext_round_rate¶

ad9361_rfpll_ext_set_rate¶

agc_adc_large_overload_exceed_counter¶

agc_adc_large_overload_inc_steps¶

agc_adc_lmt_small_overload_prevent_gain_inc_enable¶

agc_adc_small_overload_exceed_counter¶

agc_attack_delay_extra_margin_us¶

agc_dig_gain_step_size¶

agc_dig_saturation_exceed_counter¶

agc_gain_update_interval_us¶

agc_immed_gain_change_if_large_adc_overload_enable¶

agc_immed_gain_change_if_large_lmt_overload_enable¶

agc_inner_thresh_high¶

agc_inner_thresh_high_dec_steps¶

agc_inner_thresh_low¶

agc_inner_thresh_low_inc_steps¶

agc_lmt_overload_large_exceed_counter¶

agc_lmt_overload_large_inc_steps¶

agc_lmt_overload_small_exceed_counter¶

agc_outer_thresh_high¶

agc_outer_thresh_high_dec_steps¶

agc_outer_thresh_low¶

agc_outer_thresh_low_inc_steps¶

agc_sync_for_gain_counter_enable¶

aux_adc_decimation¶

aux_adc_rate¶

aux_dac1_active_in_alert_enable¶

aux_dac1_active_in_rx_enable¶

aux_dac1_active_in_tx_enable¶

aux_dac1_default_value_mV¶

aux_dac1_rx_delay_us¶

aux_dac1_tx_delay_us¶

aux_dac2_active_in_alert_enable¶

aux_dac2_active_in_rx_enable¶

aux_dac2_active_in_tx_enable¶

aux_dac2_default_value_mV¶

aux_dac2_rx_delay_us¶

aux_dac2_tx_delay_us¶

aux_dac_manual_mode_enable¶

clk_output_mode_select¶

ctrl_outs_enable_mask¶

ctrl_outs_index¶

dc_offset_attenuation_high_range¶

dc_offset_attenuation_low_range¶

dc_offset_count_high_range¶

dc_offset_count_low_range¶

dc_offset_tracking_update_event_mask¶

dcxo_coarse_and_fine_tune¶

delay_rx_data¶

digital_interface_tune_fir_disable¶

digital_interface_tune_skip_mode¶

elna_bypass_loss_mdB¶

elna_gain_mdB¶

elna_gaintable_all_index_enable¶

elna_rx1_gpo0_control_enable¶

elna_rx2_gpo1_control_enable¶

elna_settling_delay_ns¶

ensm_enable_pin_pulse_mode_enable¶

ensm_enable_txnrx_control_enable¶

external_rx_lo_enable¶

external_tx_lo_enable¶

fagc_allow_agc_gain_increase¶

fagc_dec_pow_measuremnt_duration¶

fagc_energy_lost_stronger_sig_gain_lock_exit_cnt¶

fagc_final_overrange_count¶

fagc_gain_increase_after_gain_lock_en¶

fagc_gain_index_type_after_exit_rx_mode¶

fagc_lmt_final_settling_steps¶

fagc_lock_level¶

fagc_lock_level_gain_increase_upper_limit¶

fagc_lock_level_lmt_gain_increase_en¶

fagc_lp_thresh_increment_steps¶

fagc_lp_thresh_increment_time¶

fagc_lpf_final_settling_steps¶

fagc_optimized_gain_offset¶

fagc_power_measurement_duration_in_state5¶

fagc_rst_gla_en_agc_pulled_high_en¶

fagc_rst_gla_engergy_lost_goto_optim_gain_en¶

fagc_rst_gla_engergy_lost_sig_thresh_below_ll¶

fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en¶

fagc_rst_gla_if_en_agc_pulled_high_mode¶

fagc_rst_gla_large_adc_overload_en¶

fagc_rst_gla_large_lmt_overload_en¶

fagc_rst_gla_stronger_sig_thresh_above_ll¶

fagc_rst_gla_stronger_sig_thresh_exceeded_en¶

fagc_state_wait_time_ns¶

fagc_use_last_lock_level_for_set_gain_en¶

fdd_alt_word_order_enable¶

fdd_rx_rate_2tx_enable¶

frequency_division_duplex_independent_mode_enable¶

frequency_division_duplex_mode_enable¶

full_duplex_swap_bits_enable¶

full_port_enable¶

gc_adc_large_overload_thresh¶

gc_adc_ovr_sample_size¶

gc_adc_small_overload_thresh¶

gc_dec_pow_measurement_duration¶

gc_dig_gain_enable¶

gc_lmt_overload_high_thresh¶

gc_lmt_overload_low_thresh¶

gc_low_power_thresh¶

gc_max_dig_gain¶

gc_rx1_mode¶

gc_rx2_mode¶

gpio_cal_sw1¶

gpio_cal_sw2¶

gpio_resetb¶

gpio_sync¶

gpo0_inactive_state_high_enable¶

gpo0_rx_delay_us¶

gpo0_slave_rx_enable¶

gpo0_slave_tx_enable¶

gpo0_tx_delay_us¶

gpo1_inactive_state_high_enable¶

gpo1_rx_delay_us¶

gpo1_slave_rx_enable¶

gpo1_slave_tx_enable¶

gpo1_tx_delay_us¶

gpo2_inactive_state_high_enable¶

gpo2_rx_delay_us¶

gpo2_slave_rx_enable¶

gpo2_slave_tx_enable¶

gpo2_tx_delay_us¶

gpo3_inactive_state_high_enable¶

gpo3_rx_delay_us¶

gpo3_slave_rx_enable¶

gpo3_slave_tx_enable¶

gpo3_tx_delay_us¶

half_duplex_mode_enable¶

high_gain_dB¶

id_no¶

invert_data_bus_enable¶

invert_data_clk_enable¶

invert_rx_frame_enable¶

low_gain_dB¶

low_high_gain_threshold_mdB¶

lvds_bias_mV¶

lvds_invert1_control¶

lvds_invert2_control¶

lvds_mode_enable¶

lvds_rx_onchip_termination_enable¶

mgc_dec_gain_step¶

mgc_inc_gain_step¶

mgc_rx1_ctrl_inp_enable¶

mgc_rx2_ctrl_inp_enable¶

mgc_split_table_ctrl_inp_gain_mode¶

one_rx_one_tx_mode_use_rx_num¶

one_rx_one_tx_mode_use_tx_num¶

one_shot_mode_en¶

pp_rx_swap_enable¶

pp_tx_swap_enable¶

qec_tracking_slow_mode_enable¶

reference_clk_rate¶

rf_rx_bandwidth_hz¶

rf_tx_bandwidth_hz¶

rssi_delay¶

rssi_duration¶

rssi_restart_mode¶

rssi_unit_is_rx_samples_enable¶

rssi_wait¶

rx1rx2_phase_inversion_en¶

rx_channel_swap_enable¶

rx_data_clock_delay¶

rx_data_delay¶

rx_fastlock_delay_ns¶

rx_fastlock_pincontrol_enable¶

rx_frame_pulse_mode_enable¶

rx_path_clock_frequencies¶

rx_rf_port_input_select¶

rx_synthesizer_frequency_hz¶

single_data_rate_enable¶

single_port_mode_enable¶

split_gain_table_mode_enable¶

swap_ports_enable¶

tdd_skip_vco_cal_enable¶

tdd_use_dual_synth_mode_enable¶

tdd_use_fdd_vco_tables_enable¶

temp_sense_decimation¶

temp_sense_measurement_interval_ms¶

temp_sense_offset_signed¶

temp_sense_periodic_measurement_enable¶

trx_synthesizer_target_fref_overwrite_hz¶

two_rx_two_tx_mode_enable¶

two_t_two_r_timing_enable¶

tx1_mon_front_end_gain¶

tx1_mon_lo_cm¶

tx2_mon_front_end_gain¶

tx2_mon_lo_cm¶

tx_attenuation_mdB¶

tx_channel_swap_enable¶

tx_data_delay¶

tx_fastlock_delay_ns¶

tx_fastlock_pincontrol_enable¶

tx_fb_clock_delay¶

tx_mon_delay¶

tx_mon_duration¶

tx_mon_track_en¶

tx_path_clock_frequencies¶

tx_rf_port_input_select¶

tx_synthesizer_frequency_hz¶

update_tx_gain_in_alert_enable¶

xo_disable_use_ext_refclk_enable¶

class wni.ad9361.ad9361_swig.AD9361_RXFIRConfig[source]¶

Bases: object

rx¶

rx_bandwidth¶

rx_coef¶

rx_coef_size¶

rx_dec¶

rx_gain¶

rx_path_clks¶

class wni.ad9361.ad9361_swig.AD9361_TXFIRConfig[source]¶

Bases: object

tx¶

tx_bandwidth¶

tx_coef¶

tx_coef_size¶

tx_gain¶

tx_int¶

tx_path_clks¶

class wni.ad9361.ad9361_swig.SynthLUT[source]¶

Bases: object

Charge_Pump_Current¶

LF_C1¶

LF_C2¶

LF_C3¶

LF_R1¶

LF_R3¶

VCO_Bias_Ref¶

VCO_Bias_Tcf¶

VCO_Cal_Offset¶

VCO_MHz¶

VCO_Output_Level¶

VCO_Varactor¶

VCO_Varactor_Reference¶

class wni.ad9361.ad9361_swig.ad9361_debugfs_entry[source]¶

Bases: object

cmd¶

out_value¶

phy¶

propname¶

size¶

val¶

class wni.ad9361.ad9361_swig.ad9361_fastlock[source]¶

Bases: object

current_profile¶

entry¶

save_profile¶

class wni.ad9361.ad9361_swig.ad9361_fastlock_entry[source]¶

Bases: object

alc_orig¶

alc_written¶

flags¶

class wni.ad9361.ad9361_swig.ad9361_phy_platform_data[source]¶

Bases: object

ad9361_clkout_mode¶

auxadc_ctrl¶

auxdac_ctrl¶

ctrl_outs_ctrl¶

dc_offset_attenuation_high¶

dc_offset_attenuation_low¶

dc_offset_update_events¶

dcxo_coarse¶

dcxo_fine¶

debug_mode¶

dig_interface_tune_fir_disable¶

dig_interface_tune_skipmode¶

elna_ctrl¶

ensm_pin_ctrl¶

ensm_pin_pulse_mode¶

fdd¶

fdd_independent_mode¶

gain_ctrl¶

gpio_cal_sw1¶

gpio_cal_sw2¶

gpio_resetb¶

gpio_sync¶

gpo_ctrl¶

port_ctrl¶

qec_tracking_slow_mode_en¶

rf_dc_offset_count_high¶

rf_dc_offset_count_low¶

rf_rx_bandwidth_Hz¶

rf_rx_input_sel¶

rf_tx_bandwidth_Hz¶

rf_tx_output_sel¶

rssi_ctrl¶

rx1rx2_phase_inversion_en¶

rx1tx1_mode_use_rx_num¶

rx1tx1_mode_use_tx_num¶

rx2tx2¶

rx_fastlock_delay_ns¶

rx_path_clks¶

rx_synth_freq¶

split_gt¶

tdd_skip_vco_cal¶

tdd_use_dual_synth¶

tdd_use_fdd_tables¶

trx_fastlock_pinctrl_en¶

trx_synth_max_fref¶

tx_atten¶

tx_fastlock_delay_ns¶

tx_path_clks¶

tx_synth_freq¶

txmon_ctrl¶

update_tx_gain_via_alert¶

use_ext_rx_lo¶

use_ext_tx_lo¶

use_extclk¶

class wni.ad9361.ad9361_swig.ad9361_rf_phy[source]¶

Bases: object

ad9361_rfpll_ext_recalc_rate¶

ad9361_rfpll_ext_round_rate¶

ad9361_rfpll_ext_set_rate¶

adc_conv¶

adc_state¶

agc_mode¶

auto_cal_en¶

auxdac1_value¶

auxdac2_value¶

bbdc_track_en¶

bist_loopback_mode¶

bist_prbs_mode¶

bist_tone_freq_Hz¶

bist_tone_level_dB¶

bist_tone_mask¶

bist_tone_mode¶

bypass_rx_fir¶

bypass_tx_fir¶

cached_rx_rfpll_div¶

cached_tx_rfpll_div¶

cal_threshold_freq¶

clk_data¶

clk_refin¶

clks¶

curr_ensm_state¶

current_rx_bw_Hz¶

current_table¶

current_tx_bw_Hz¶

ensm_pin_ctl_en¶

fastlock¶

filt_rx_bw_Hz¶

filt_rx_path_clks¶

filt_tx_bw_Hz¶

filt_tx_path_clks¶

filt_valid¶

flags¶

id_no¶

last_tx_quad_cal_freq¶

last_tx_quad_cal_phase¶

pdata¶

prev_ensm_state¶

quad_track_en¶

rate_governor¶

ref_clk_scale¶

rfdc_track_en¶

rx_eq_2tx¶

rx_fir_dec¶

rx_fir_ntaps¶

rx_gain¶

rxbbf_div¶

spi¶

tx_fir_int¶

tx_fir_ntaps¶

txmon_tdd_en¶

class wni.ad9361.ad9361_swig.auxadc_control[source]¶

Bases: object

auxadc_clock_rate¶

auxadc_decimation¶

offset¶

periodic_temp_measuremnt¶

temp_sensor_decimation¶

temp_time_inteval_ms¶

class wni.ad9361.ad9361_swig.auxdac_control[source]¶

Bases: object

auxdac_manual_mode_en¶

dac1_default_value¶

dac1_in_alert_en¶

dac1_in_rx_en¶

dac1_in_tx_en¶

dac1_rx_delay_us¶

dac1_tx_delay_us¶

dac2_default_value¶

dac2_in_alert_en¶

dac2_in_rx_en¶

dac2_in_tx_en¶

dac2_rx_delay_us¶

dac2_tx_delay_us¶

class wni.ad9361.ad9361_swig.axiadc_chip_info[source]¶

Bases: object

max_rate¶

name¶

num_channels¶

class wni.ad9361.ad9361_swig.axiadc_converter[source]¶

Bases: object

chip_info¶

scratch_reg¶

class wni.ad9361.ad9361_swig.axiadc_state[source]¶

Bases: object

pcore_version¶

phy¶

class wni.ad9361.ad9361_swig.bist_tone[source]¶

Bases: object

freq_Hz¶

level_dB¶

mask¶

mode¶

class wni.ad9361.ad9361_swig.clk[source]¶

Bases: object

name¶

rate¶

class wni.ad9361.ad9361_swig.clk_hw[source]¶

Bases: object

clk¶

class wni.ad9361.ad9361_swig.clk_init_data[source]¶

Bases: object

flags¶

name¶

num_parents¶

ops¶

parent_names¶

class wni.ad9361.ad9361_swig.clk_onecell_data[source]¶

Bases: object

clk_num¶

clks¶

class wni.ad9361.ad9361_swig.ctrl_outs_control[source]¶

Bases: object

en_mask¶

index¶

class wni.ad9361.ad9361_swig.device[source]¶: Bases: object

class wni.ad9361.ad9361_swig.elna_control[source]¶

Bases: object

bypass_loss_mdB¶

elna_1_control_en¶

elna_2_control_en¶

elna_in_gaintable_all_index_en¶

gain_mdB¶

settling_delay_ns¶

class wni.ad9361.ad9361_swig.gain_control[source]¶

Bases: object

adc_large_overload_exceed_counter¶

adc_large_overload_inc_steps¶

adc_large_overload_thresh¶

adc_lmt_small_overload_prevent_gain_inc¶

adc_ovr_sample_size¶

adc_small_overload_exceed_counter¶

adc_small_overload_thresh¶

agc_attack_delay_extra_margin_us¶

agc_inner_thresh_high¶

agc_inner_thresh_high_dec_steps¶

agc_inner_thresh_low¶

agc_inner_thresh_low_inc_steps¶

agc_outer_thresh_high¶

agc_outer_thresh_high_dec_steps¶

agc_outer_thresh_low¶

agc_outer_thresh_low_inc_steps¶

dec_pow_measuremnt_duration¶

dig_gain_en¶

dig_gain_step_size¶

dig_saturation_exceed_counter¶

f_agc_allow_agc_gain_increase¶

f_agc_dec_pow_measuremnt_duration¶

f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt¶

f_agc_final_overrange_count¶

f_agc_gain_increase_after_gain_lock_en¶

f_agc_gain_index_type_after_exit_rx_mode¶

f_agc_lmt_final_settling_steps¶

f_agc_lock_level¶

f_agc_lock_level_gain_increase_upper_limit¶

f_agc_lock_level_lmt_gain_increase_en¶

f_agc_lp_thresh_increment_steps¶

f_agc_lp_thresh_increment_time¶

f_agc_lpf_final_settling_steps¶

f_agc_optimized_gain_offset¶

f_agc_power_measurement_duration_in_state5¶

f_agc_rst_gla_en_agc_pulled_high_en¶

f_agc_rst_gla_engergy_lost_goto_optim_gain_en¶

f_agc_rst_gla_engergy_lost_sig_thresh_below_ll¶

f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en¶

f_agc_rst_gla_if_en_agc_pulled_high_mode¶

f_agc_rst_gla_large_adc_overload_en¶

f_agc_rst_gla_large_lmt_overload_en¶

f_agc_rst_gla_stronger_sig_thresh_above_ll¶

f_agc_rst_gla_stronger_sig_thresh_exceeded_en¶

f_agc_state_wait_time_ns¶

f_agc_use_last_lock_level_for_set_gain_en¶

gain_update_interval_us¶

immed_gain_change_if_large_adc_overload¶

immed_gain_change_if_large_lmt_overload¶

lmt_overload_high_thresh¶

lmt_overload_large_exceed_counter¶

lmt_overload_large_inc_steps¶

lmt_overload_low_thresh¶

lmt_overload_small_exceed_counter¶

low_power_thresh¶

max_dig_gain¶

mgc_dec_gain_step¶

mgc_inc_gain_step¶

mgc_rx1_ctrl_inp_en¶

mgc_rx2_ctrl_inp_en¶

mgc_split_table_ctrl_inp_gain_mode¶

rx1_mode¶

rx2_mode¶

sync_for_gain_counter_en¶

class wni.ad9361.ad9361_swig.gpo_control[source]¶

Bases: object

gpo0_inactive_state_high_en¶

gpo0_rx_delay_us¶

gpo0_slave_rx_en¶

gpo0_slave_tx_en¶

gpo0_tx_delay_us¶

gpo1_inactive_state_high_en¶

gpo1_rx_delay_us¶

gpo1_slave_rx_en¶

gpo1_slave_tx_en¶

gpo1_tx_delay_us¶

gpo2_inactive_state_high_en¶

gpo2_rx_delay_us¶

gpo2_slave_rx_en¶

gpo2_slave_tx_en¶

gpo2_tx_delay_us¶

gpo3_inactive_state_high_en¶

gpo3_rx_delay_us¶

gpo3_slave_rx_en¶

gpo3_slave_tx_en¶

gpo3_tx_delay_us¶

class wni.ad9361.ad9361_swig.port_control[source]¶

Bases: object

digital_io_ctrl¶

lvds_bias_ctrl¶

lvds_invert¶

pp_conf¶

rx_clk_data_delay¶

tx_clk_data_delay¶

class wni.ad9361.ad9361_swig.refclk_scale[source]¶

Bases: object

div¶

mult¶

parent_source¶

phy¶

source¶

spi¶

class wni.ad9361.ad9361_swig.rf_gain_ctrl[source]¶

Bases: object

ant¶

mode¶

class wni.ad9361.ad9361_swig.rf_rssi[source]¶

Bases: object

ant¶

duration¶

multiplier¶

preamble¶

symbol¶

class wni.ad9361.ad9361_swig.rf_rx_gain[source]¶

Bases: object

ant¶

digital_gain¶

fgt_lmt_index¶

gain_db¶

lmt_gain¶

lna_index¶

lpf_gain¶

mixer_index¶

tia_index¶

class wni.ad9361.ad9361_swig.rssi_control[source]¶

Bases: object

restart_mode¶

rssi_delay¶

rssi_duration¶

rssi_unit_is_rx_samples¶

rssi_wait¶

class wni.ad9361.ad9361_swig.rx_gain_info[source]¶

Bases: object

gain_step_db¶

idx_step_offset¶

max_gain_db¶

max_idx¶

starting_gain_db¶

tbl_type¶

class wni.ad9361.ad9361_swig.spi_device[source]¶

Bases: object

dev¶

id_no¶

class wni.ad9361.ad9361_swig.tx_monitor_control[source]¶

Bases: object

high_gain_dB¶

low_gain_dB¶

low_high_gain_threshold_mdB¶

one_shot_mode_en¶

tx1_mon_front_end_gain¶

tx1_mon_lo_cm¶

tx2_mon_front_end_gain¶

tx2_mon_lo_cm¶

tx_mon_delay¶

tx_mon_duration¶

tx_mon_track_en¶

wni.ad9361¶

Submodules¶

wni.ad9361.ad9361¶

wni.ad9361.ad9361_swig¶

Module contents¶